To reduce capacitive loading on conventional electrostatic discharge protection circuits, a diode 10 is employed in series with the main clamp 20 to protect an input buffer 30 connected to pad or node 32 as shown in FIG. 1. Main clamp 20 is an MOS transistor comprising a source 22, a drain 24, a body 26 and a gate 28. Source 22 and body 26 are connected to ground; and drain 24 is connected to the cathode of diode 10. The anode of diode 10 is connected to pad 32. During normal operation, the drain of the main clamp is pulled to Vcc by diode 40 and resistor 45 to avoid forward biasing diode 10. Gate 28 of the main clamp is soft grounded through a transistor 50 to facilitate bipolar triggering. An additional diode 90 is frequently connected between pad 32 and ground with its cathode connected to pad 32 and its anode to ground. Diode 90 is typically formed at the junction between a p+ diffusion region and an n-well. Diode 90 provides for discharge of negative electrostatic events.
While such circuit can be employed in older technologies, where input buffers use relatively thick gate oxides, guaranteeing the survivability of this oxide to ESD events in 65 nm technologies and beyond constitutes a significant challenge. Of particular concern are charge device model (CDM) discharges where dangerous high voltages can appear directly on the gate of the input buffer. Any attempt to increase the size of the series diode and or the mosfet clamp with the intent to decrease such voltage overshoots will inevitably lead to an increase of the capacitive loading on the pad limiting the input bandwidth.